The present invention relates to systems and methods for the recovery of asynchronous digital data by a receiver, and more particularly to an apparatus and method for detecting and identifying an intermittent loss of data in the recovered data signal.
In digital data transmission systems operating in an asynchronous data transfer mode, digital data is output by a transmission unit as an asynchronous serial data signal, without a clock signal embedded therein. Upon reception of the asynchronous serial data signal, the receiver must function to recover the data transmitted by the transmission unit, and to generate a clock signal corresponding to the received data. Importantly, both the generated clock signal and the data must be synchronous (i.e., phase aligned) with one another so as to allow the receiver to properly process the received data.
FIG. 1 illustrates an example of a prior art clock and data regeneration portion of a receiver circuit. As shown, the receiver 10 has a cable 8 coupled to the input thereof. Cable 8 functions to couple the asynchronous data signal to the receiver. The clock and data regeneration portion 12 of the receiver comprises a clock recovery unit 13 and a sampling gate 14, which, for example, can comprise a flip-flop. In operation, the incoming serial data signal is coupled to the clock recovery unit 13, which functions to reproduce a clock signal corresponding to the received data signal. The output of the clock recovery unit 13 is coupled to a clock input of the sampling gate 14, and is utilized to clock the sampling gate 14. As such, the output of the sampling flip-flop 14 and the clock recovery unit 13 represent the incoming data signal and corresponding clock signal phase aligned with one another. These two signals, which represent the output of the clock and data regeneration portion 12 of the receiver, are coupled to the main portion of the receiver for processing.
FIG. 2 illustrates an example of known clock recovery unit 16. As shown, the clock recovery unit comprises a phase detector 17, a charge pump 18, a low pass filter 19 and a voltage controller oscillator (xe2x80x9cVCOxe2x80x9d) 20 all coupled in series. In operation, the phase detector 17 receives both the incoming serial data signal and the output of the VCO 20 as input signals, and detects the phase difference between these two signals. The phase difference output by the phase detector 17 is then utilized to control the voltage level output by the charge pump 18 so as to adjust the frequency of the signal output by the VCO 20 to eliminate the phase difference between the VCO 20 and the incoming serial data signal. Accordingly, the output of the VCO 20 is continuously tracking the incoming serial data signal and represents the recovered clock signal.
While known receiver systems can identify a disruption in incoming data, for example, resulting from a break in the transmission line, currently, there is no known method for identifying an error of a sole bit of data, with regard to either the generated clock signal or the sampled data signal, in an efficient and cost effective manner. In other words, there is no known system for identifying that a given sampled signal (i.e., data and clock) is in error. Accordingly, there is exists a need for an error detection system that can readily identify when an error has occurred in the regeneration of the data signal or the corresponding clock signal so that the system does not process erroneous data. Furthermore, it is necessary that the system be simple and cost effective so that it is practical to include the error detection system in today""s generation of the asynchronous data receivers.
In an effort to solve the aforementioned needs, it is an object of the present invention to provide a simple, cost effective design that provides for error detection of the received data signal and the corresponding clock signal.
More specifically, the present invention relates to an error detection circuit comprising a first counter for receiving a data signal, where the first counter is operative for counting each pulse contained in the data signal; a second counter for receiving a sampled data signal, where the second counter is operative for counting each pulse contained in the sampled data signal; a subtractor circuit for subtracting the value of the second counter from the value of the first counter, and for generating a result value; and an error indication circuit for monitoring the result value of the subtractor circuit and for generating an error signal when the result value exceeds a predetermined value.
The present invention further relates to a receiver operative for receiving an asynchronous digital data signal. The receiver comprises a clock recovery unit operative for receiving the asynchronous serial data signal and for producing a clock signal corresponding to the asynchronous serial data signal; a sampling gate operative for receiving the asynchronous serial data signal and the clock signal as input signals, and for producing a sampled data signal, where the sampled data signal corresponds to the asynchronous serial data signal and is synchronized with the clock signal; a first counter for receiving the asynchronous serial data signal and operative for counting each pulse contained in the asynchronous serial data signal; a second counter for receiving the sampled data signal and for counting each pulse contained in the sampled data signal; a subtractor circuit for subtracting the value of the second counter from the value of the first counter, and for generating a result value; and an error indication circuit for monitoring the result value of the subtractor and for generating an error signal when the result value exceeds a predetermined value.
As described in further detail below, the present invention provides significant advantages over the prior art. Most importantly, the error detection system of the present invention provides a simple and cost efficient method of identifying if even a sole bit of the received data and the corresponding clock signal are in error. Thus, the system provides for improved reliability in a practical manner, which can be readily implemented in asynchronous serial data receivers.
Additional advantages of the present invention will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the present invention.